Down converters in wireless receivers perform a transformation of a radio frequency (RF) signal into a baseband signal centered at the zero frequency. In high performance equipment, digital down converters are used, making it necessary to convert an analog RF signal into a digital signal. Typically, a high speed ADC is used because of the high frequency of the RF signal.
High speed analog to digital converters are built as composite ADCs that consist of a number of interleaved sub-ADCs with a common input and sequential timing. In general, the amplitude and phase frequency responses of the different sub-ADCs are not identical, resulting in specific signal distortions, for example, the appearance of spurious frequency components. To prevent these distortions, equalization of the responses of the sub-ADCs is used (see, for example, U.S. Pat. No. 7,408,495).
A block diagram of a conventional digital down converter with an equalizer is shown in FIG. 1. In the digital down converter of FIG. 1, an RF signal, applied to the input of a composite ADC, is transformed into a digital signal. The misalignment of the frequency responses of the sub-ADCs of the ADC, is corrected by an equalizer. The corrected signal is applied to an I/Q demodulator constructed using two mixers with the same local oscillator frequency and with a phase difference of 90°. The resultant demodulated signals are applied to low pass filters (LPF-I and LPF-Q) with following decimators (Decimator-I and Decimator-Q, producing two outputs: In-Phase (I) and Quadrature (Q), labeled Output I and Output Q, respectively, in FIG. 1.
The ADC equalizer and low pass filters in the block diagram of FIG. 1 are built usually as conventional FIR filters. The most resource-consuming components of the FIR filters are multipliers. Because of the difference between the RF signal frequency (usually several GHz) and the frequency of operation of present-day computing devices (up to 200-250 MHz for an FPGA, for example), each multiplication in the FIR is carried out by a group of multipliers connected in parallel. The required number of multipliers becomes the main reason that makes it necessary to use in the equalizer design, large amounts of computing resources or, in some cases, makes a real time equalizer design impossible.
It is possible to reduce to some extent, the required number of multipliers in the conventional down converter of the type shown in FIG. 1, by embedding the decimation function within the low pass filters between the principal shift register of the FIR and the multipliers (see, for example, J. G. Proakis and D. G. Manolakis, “Digital Signal Processing: Principles, Algorithms, and Applications”, 3rd Edition, Prentice-Hall International Inc., pp. 793-797). In such a design, the multiplications in the low pass filters are performed at lower sampling rates, with a consequent possibility to reduce the required number of multipliers. However, the number of multipliers in the equalizer far exceeds the number of multipliers in the low pass filters. For this reason, a reduction of the number of multipliers only in the filters, does not lead to a substantial decrease of the total number of multipliers in the down converter.
A down converter with a reduced number of multipliers was suggested in U.S. Pat. No. 9,148,162. In a down converter according to the '162 patent, equalization is combined with down conversion and performed in I and Q branches separately. Furthermore, three cascade-connected units in each branch (equalizer, mixer and low pass filter) are replaced by a single equivalent finite impulse response filter (FIR). A decimator is placed inside that FIR before the multipliers. As a result, the frequency of each multiplication in the down converter is lowered and the number of required multipliers is reduced significantly.
A block diagram of a digital down converter with equalization in accordance with U.S. Pat. No. 9,148,162 is shown in FIG. 2. The block diagram has an analog input, a sampling clock input and two outputs: output I and output Q. The digital down converter of the '162 patent comprises an analog to digital converter (ADC), a frequency divider, two FIRs with time variant coefficients and built-in decimators: FIR-decimator-I and FIR-decimator-Q, and a frequency corrector. The analog to digital converter transforms the input analog signal into a digital signal. The frequency divider receives the sampling clock and produces a low frequency clock (LF_Clock) with a frequency that equals the frequency of the sampling clock divided by a decimation factor. Successful operation of the digital down converter is achieved by loading into the FIR-decimator-I and FIR-decimator-Q properly calculated coefficients.
The reduction of the number of required multipliers in the block diagram of FIG. 2 makes it possible to build digital down converters that operate in a real time mode even in high frequency receivers. However, the described digital down converter has drawbacks that make difficult to achieve successful use.
In particular, the down converter according to FIG. 2 is able to correct only frequency responses that are symmetrical relative a local oscillator (LO) frequency FLO: the loss and change in phase should be the same at frequencies FLO−f and FLO+f. However, sub-ADCs in a composite ADC may be asymmetric with regard to an LO frequency of the down converter. As a consequence, ADCs cannot be equalized by the configuration set forth in the block diagram of FIG. 2.
The FIR-decimators incorporated in the block diagram of FIG. 2 necessarily include shift registers that operate with the sampling rate of the ADC. As a consequence, one cannot implement a down converter using conventional computing devices with speed of operation that is less than sampling rate of an ADC.
It is desirable to provide an improved digital down converter, which is able to equalize asymmetrical frequency responses, as well as symmetrical ones, and makes possible implementation by conventional computing devices.